Layout Design on Multi-finger Mosfet for On-chip Esd Protection Circuits in a 0.18-μm Salicided Cmos Process
نویسندگان
چکیده
The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18-μm salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more compactly, but still to provide deep-submicron CMOS IC’s with higher ESD robustness.
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